Thin film transistor array panel, manufacturing method thereof, and mask therefor

ABSTRACT

A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

BACKGROUND OF THE INVENTION

[0001] (a) Field of the Invention The present invention relates to athin film transistor array panel, a manufacturing method thereof, and amask therefor.

[0002] (b) Description of the Related Art

[0003] Liquid crystal displays (LCDs) are one of the most widely usedflat panel displays. An LCD includes two panels provided withfield-generating electrodes and a liquid crystal (LC) layer interposedtherebetween. The LCD displays images by applying voltages to thefield-generating electrodes to generate an electric field in the LClayer, which determines orientations of LC molecules in the LC layer toadjust polarization of incident light.

[0004] Among LCDs including field-generating electrodes on respectivepanels, a kind of LCDs provides a plurality of pixel electrodes arrangedin a matrix at one panel and a common electrode covering an entiresurface of the other panel. The image display of the LCD is accomplishedby applying individual voltages to the respective pixel electrodes. Forthe application of the individual voltages, a plurality ofthree-terminal thin film transistors (TFTs) are connected to therespective pixel electrodes, and a plurality of gate lines transmittingsignals for controlling the TFTs and a plurality of data linestransmitting voltages to be applied to the pixel electrodes are providedon the panel.

[0005] The panel for an LCD has a layered structure including severalconductive layers and several insulating layers. The gate lines, thedata lines, and the pixel electrodes are made from different conductivelayers (referred to as “gate conductor,” “data conductor,” and “pixelconductor” hereinafter) preferably deposited in sequence and separatedby insulating layers. A TFT includes three electrodes: a gate electrodemade from the gate conductor and source and drain electrodes made fromthe data conductor. The source electrode and the drain electrode areconnected by a semiconductor usually located thereunder, and the drainelectrode is connected to the pixel electrode through a hole in aninsulating layer.

[0006] The gate conductor and the data conductor are preferably made ofAl containing metal such as Al and Al alloy having low resistivity forreducing the signal delay in the gate lines and the data lines. Thepixel electrodes are usually made of transparent conductive materialsuch as indium tin oxide (ITO) and indium zinc oxide (IZO) for both thefield generation upon voltage application and the light transmission.

[0007] In the meantime, the contact between Al containing metal and ITOor IZO causes several problems such as corrosion of the Al containingmetal and the large contact resistance.

[0008] As described above, a drain electrode and a pixel electrode areconnected through a contact hole in an insulator. This connection isobtained by forming the hole in the insulator to expose a portion of anupper Al-containing metal layer of the drain electrode, removing theexposed portions of the upper metal layer by blanket-etching to expose alower layer having good contact characteristic, and finally, forming thepixel electrode thereon. However, the blanket etch frequently generatesundercut formed by over-etching the Al containing metal under a sidewallof the contact hole. The undercut yields disconnection or poor profileof the subsequently-formed pixel electrode near the undercut to increasethe contact resistance between the pixel electrode and the drainelectrode.

SUMMARY OF THE INVENTION

[0009] A thin film transistor array panel is provided, which includes: agate line formed on an insulating substrate; a gate insulating layer onthe gate conductive layer; a semiconductor layer on the gate insulatinglayer; a data line formed on the gate insulating layer and including aportion disposed on the semiconductor layer; a passivation layer formedon the data line and having a first contact hole exposing at least aportion of a boundary of the gate line or the data line; and a contactassistant formed on the passivation layer and on the exposed portion ofthe boundary of the gate line or the data line.

[0010] At least one of the gate line, the data line, and the drainelectrode preferably includes a lower film of Cr, Mo or Mo alloy and anupper film of Al or Al alloy, and the contact assistant, preferablyincluding ITO or IZO, is preferably in contact with the lower film.

[0011] The thin film transistor array panel may further includes: adrain electrode separated from the data line and formed on the gateinsulating layer and the semiconductor layer; and a pixel electrodeformed on the passivation layer and connected to the drain electrodethrough a second contact hole.

[0012] An exposure mask is provided, which includes: an opaque areablocking light; and a slit pattern formed in the opaque area andincluding a plurality of slits, wherein the slits are substantiallyrectilinear, and width of each slit and distance between the slits arein a range about 0.8-2.0 microns.

[0013] The slits may have depressions.

[0014] The mask may be utilized in manufacturing a thin film transistorpanel including a display area where a plurality of signal linesintersect each other and a peripheral area where end portions of thesignal lines are disposed. The slits may include first slits in thedisplay area and second slits in the peripheral area, and the first andthe second slits have different width and distance.

[0015] The slits may include first slits in the display area and in theperipheral area and second slits in a remaining area, and the first andthe second slits have different width and distance.

[0016] A method of manufacturing a thin film transistor array panel isprovided, the method includes: forming a gate line on an insulatingsubstrate; forming a gate insulating layer; forming a semiconductormember; forming a data conductive layer including a data line and adrain electrode; forming a passivation layer having a contact holeexposing at least a portion of the drain electrode and a portion of thegate insulating layer near an edge of the drain electrode; and forming apixel electrode connected to the drain electrode through the contacthole, wherein at least one of the semiconductor member and thepassivation layer is patterned by photolithography using a mask having aplurality of substantially rectilinear slits and width of each slit anddistance between the slits range from about 0.8 to about 2.0 microns.

[0017] The mask may include a first area blocking light, a second areaprovided with the slits for partially transmitting light, and a thirdarea fully transmitting light.

[0018] The photolithography may form a positive photoresist including afirst portion on the data line and a first portion of the drainelectrode, a second portion on a second portion of the drain electrode,and a third portion on an end portion of the gate line. The secondportion of the photoresist is thinner than the first portion of thephotoresist, and the third portion of the photoresist is thinner thanthe second portions of the photoresist.

[0019] The photoresist may further include a fourth portion on an endportion of the data line and having a thickness smaller than the firstportion of the photoresist.

[0020] The method may further include: performing etching using thephotoresist to expose portions of the passivation layer under the secondand the fourth portions of the photoresist and a portion of the gateinsulating layer under the third portion; and removing the exposedportions of the passivation layer and the gate insulating layer to formcontact holes exposing the end portions of the gate line and the dataline.

[0021] The slits may include first slits corresponding to the secondportion of the photoresist and second slits corresponding to the fourthportion of the photoresist, and the first and the second slits havedifferent width and distance.

[0022] The patterning of at least one of the semiconductor member andthe passivation layer by photolithography may include: depositing asemiconductor layer on the gate insulating layer; depositing aninsulating layer on the data conductive layer; forming the photoresiston the insulating layer; performing etching using the photoresist toexpose portions of the passivation layer under the second and the fourthportions of the photoresist and a portion of the gate insulating layerunder the third portion; removing the exposed portions of thepassivation layer and the gate insulating layer to form contact holesexposing the end portions of the gate line and the data line and toexpose portions of the semiconductor layer; and removing the exposedportions of the semiconductor layer to form the semiconductor member.

[0023] The semiconductor member may include a plurality of semiconductorportions separated from each other at positions between adjacent datalines.

[0024] The thin film transistor panel may include a display area wherethe gate line intersects the data line and a peripheral area where endportions of the gate line and the data line are disposed, the slitsinclude first slits in the display area and in the peripheral area andsecond slits in a remaining area, and the first and the second slitshave different width and distance.

[0025] At least one of the gate line and the data conductive layer mayinclude a lower film of Cr, Mo or Mo alloy and an upper film of Al or Alalloy.

[0026] The drain electrode may include the lower film and the upper filmand the method further include: removing the upper film of the at leasta portion of the drain electrode before forming the pixel electrode.

[0027] The mask may be aligned such that at least one of the slitsoverlaps a boundary of the drain electrode, and the at least one of theslits may have a depression.

[0028] The mask may be aligned such that at least two of the slits aredisposed out of the drain electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will become more apparent by describingembodiments thereof in detail with reference to the accompanyingdrawings in which:

[0030]FIG. 1 is a schematic diagram of a substrate for LCD according toan embodiment of the present invention;

[0031]FIG. 2 is a schematic layout view of a TFT array panel for an LCDaccording to an embodiment of the present invention;

[0032]FIG. 3 is a layout view of an exemplary TFT array panel for an LCDaccording to an embodiment of the present invention;

[0033]FIG. 4 is a sectional view of the TFT array panel shown in FIG. 3taken along the line IV-IV′;

[0034]FIGS. 5A, 6A, 7A and 9A are layout views of the TFT array panelshown in FIGS. 1-4 in intermediate steps of a manufacturing methodthereof according to an embodiment of the present invention;

[0035]FIGS. 5B, 6B, 7B and 9B are sectional views of the TFT array panelshown in FIGS. 5A, 6A, 7A and 9A taken along the lines VB-VB′, VIB-VIB′,VIIB-VIIB′, and IX-IX′, respectively;

[0036]FIG. 8 is a sectional view of the TFT array panel shown in FIG. 7Ataken along the line VII-VII′ in the step of the manufacturing methodfollowing the step shown in FIG. 7B;

[0037]FIG. 10 illustrates alignment between slits of a mask and a drainelectrode;

[0038]FIGS. 11 and 12 are sectional views of the TFT array panel shownin FIG. 9A in the steps of the manufacturing method following the stepshown in FIG. 9B.

[0039]FIG. 13 is a layout view of an exemplary TFT array panel for anLCD according to another embodiment of the present invention;

[0040]FIGS. 14 and 15 are sectional views of the TFT array panel shownin FIG. 13 taken along the line XIV-XIV′ and the line XV-XV′,respectively;

[0041]FIG. 16A is a layout view of a TFT array panel shown in FIGS.13-15 in the first step of a manufacturing method thereof according toan embodiment of the present invention;

[0042]FIGS. 16B and 16C are sectional views of the TFT array panel shownin FIG. 16A taken along the lines XVIB-XVIB′ and XVIC-XVIC′,respectively;

[0043]FIGS. 17A and 17B are sectional views of the TFT array panel shownin FIG. 16A taken along the lines XVIB-XVIB′ and XVIC-XVIC′,respectively, and illustrate the step following the step shown in FIGS.16B and 16C;

[0044]FIG. 18A is a layout view of the TFT array panel in the stepfollowing the step shown in FIGS. 17A and 17B;

[0045]FIGS. 18B and 18C are sectional views of the TFT array panel shownin FIG. 18A taken along the lines XVIIIB-XVIIIB′ and XVIIIC-XVIIIC′,respectively;

[0046]FIGS. 19A, 20A and 21A and FIGS. 19B, 20B and 21B are respectivesectional views of the TFT array panel shown in FIG. 18A taken along thelines XVIIIB-XVIIIB′ and XVIIIC-XVIIIC′, respectively, and illustratethe steps following the step shown in FIGS. 18B and 18C;

[0047]FIG. 22A is a layout view of a TFT array panel in the stepfollowing the step shown in FIGS. 21A and 21B;

[0048]FIGS. 22B and 22C are sectional views of the TFT array panel shownin FIG. 22A taken along the lines XXIIB-XXIIB′ and XXIIC-XXIIC′,respectively;

[0049]FIGS. 23A, 24A and 25A and FIGS. 23B, 24B and 25B are respectivesectional views of the TFT array panel shown in FIG. 22A taken along thelines XXIIB-XXIIB′ and XXIIC-XXIIC′, respectively, and illustrate thesteps following the step shown in FIGS. 22B and 22C;

[0050]FIG. 26 is a layout view of an exemplary TFT array panel for anLCD according to another embodiment of the present invention;

[0051]FIG. 27 is a sectional view of the TFT array panel shown in FIG.26 taken along the line XXVII-XXVII′;

[0052]FIGS. 28A, 29A and 30A are layout views of the TFT array panelshown in FIGS. 26 and 27 in intermediate steps of a manufacturing methodthereof according to an embodiment of the present invention;

[0053]FIGS. 28B, 29B and 30B are sectional views of the TFT array panelshown in FIGS. 28A, 29A and 30A taken along the lines XXVIIIB-XXVIIIB′,XXIXB-XXIXB′, and XXX-XXX′, respectively;

[0054]FIGS. 31 and 32 are sectional views of the TFT array panel shownin FIG. 30A taken along the line XXXB-XXXB′ in the steps of themanufacturing method following the step shown in FIG. 30B;

[0055]FIG. 33 is a layout view of an exemplary TFT array panel for anLCD according to another embodiment of the present invention; and

[0056]FIG. 34 is a sectional view of the TFT array panel shown in FIG.33 taken along the line XXXIV-XXXIV′.

DETAILED DESCRIPTION OF EMBODIMENTS

[0057] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. The present inventionmay, however, be embodied in many different forms and should not beconstrued as limited to the embodiments set forth herein.

[0058] In the drawings, the thickness of layers, films and regions areexaggerated for clarity. Like numerals refer to like elementsthroughout. It will be understood that when an element such as a layer,film, region or substrate is referred to as being “on” another element,it can be directly on the other element or intervening elements may alsobe present. In contrast, when an element is referred to as being“directly on” another element, there are no intervening elementspresent.

[0059] Now, TFT array panels and manufacturing methods thereof accordingto embodiments of the present invention will be described with referenceto the accompanying drawings.

[0060]FIG. 1 is a schematic diagram of a substrate for LCD according toan embodiment of the present invention.

[0061] Referring to FIG. 1, a substrate 100 preferably made of glassincludes a plurality of, for example, four device areas 10-40. When thesubstrate 100 is prepared for TFT array panels, each device area 1040includes a display area 11-41 provided with a plurality of pixel areasand a peripheral area 12-42. The display area 11-41 is provided with aplurality of TFTs, signal lines, and pixel electrodes, which arearranged in a matrix, and the peripheral area 12-42 is provided withelements such as pads of the signal lines, which will be connected toexternal driving devices, and electrostatic discharge protectioncircuits.

[0062] The elements of the LCD are formed preferably using an exposercalled stepper. When using the stepper, the display area 11-41 and theperipheral area 12-42 are divided by several exposure areas (havingboundaries indicated by dotted lines in FIG. 1), portions of aphotoresist film (not shown) on the exposure areas are separatelyexposed to light through the same or different exposure masks.Subsequently, the photoresist film is developed to form a photoresistpattern and a layer under the photoresist pattern is etched to form apredetermined pattern. A TFT array panel for an LCD is completed by therepeated formation of the layer patterns.

[0063]FIG. 2 is a schematic layout view of a TFT array panel for an LCDaccording to an embodiment of the present invention.

[0064] Referring to FIG. 2, a plurality of TFTs 3, a plurality of pixelelectrodes 191 electrically connected to the TFTs 3, a plurality ofsignal lines including mutually intersecting gate lines 121 and datalines 171 are disposed in a display area surrounded by lines 1. In aperipheral area disposed out of the display area, expansions 125 and 179of the gate lines 121 and the data lines 179 are disposed to beconnected to gate driving ICs and data driving ICs for receiving signalsto be applied to the gate lines 121 and the data lines 171. In addition,a gate shorting bar 124 and a data shorting bar 174, which areelectrically connected to the gate lines 121 and the data lines 171,respectively, and a shorting bar connection 194 connected to theshorting bars 124 and 174 are provided in the peripheral area, and theymake the gate lines 121 and the data lines 171 have equal potential toprevent device breakdown due to electrostatic discharge. The shortingbars 124 and 174 are electrically disconnected from the gate lines 121and the data lines 171 at a later time by scribing the substrate 100along a line 2. Although it is not shown in the figure, insulator(s) isinterposed between the shorting bar connection 194 and the shorting bars124 and 174 and contact holes for connecting the connection 194 and theshorting bars 124 and 174 are provided at the insulator. In addition, aninsulator is disposed between the TFT 3 and the pixel electrode 191 anda contact hole for connecting the TFT3 and the pixel electrode 191 isprovided at the insulator.

First Embodiment

[0065] A TFT array panel for an LCD will be described in detail withreference to FIGS. 3 and 4 as well as FIGS. 1 and 2.

[0066] A TFT array panel for an LCD will be described in detail withreference to FIGS. 3 and 4 as well as FIGS. 1 and 2.

[0067]FIG. 3 is an exemplary layout view of TFTs, pixel electrodes,portions of signal lines located on the display area and expansions ofthe signal lines located on the peripheral area of the exemplary TFTarray panel shown in FIG. 2 according to an embodiment of the presentinvention, and FIG. 4 is a sectional view of the TFT array panel shownin FIG. 3 taken along the line IV-IV′.

[0068] A plurality of gate lines 121 for transmitting gate signals and agate shorting bar 124 extending substantially in a longitudinaldirection are formed on an insulating substrate 110. Each gate line 121extends substantially in a transverse direction and a plurality ofportions of each gate line 121 form a plurality of gate electrodes 123.Each gate line 121 includes a plurality of projections 127 protrudingdownward, an expansion 125 having wider width for contact with anotherlayer or an external device, and an extension 126 connected between theexpansion 125 and the gate shorting bar 124. Most portions of the gatelines 121 are disposed on the display area, while the expansions 125 andthe extensions 126 of the gate lines 121 as well as the gate shortingbar 124 are disposed on the peripheral area.

[0069] The gate lines 121 as well as the gate shorting bar 124 includetwo films having different physical characteristics, a lower film 121 pand an upper film 121 q. The upper film 121 q is preferably made of lowresistivity metal including Al containing metal such as Al and Al alloyfor reducing signal delay or voltage drop in the gate lines 121. On theother hand, the lower film 121 p is preferably made of material such asCr, Mo, Mo alloy, Ta and Ti, which has good physical, chemical, andelectrical contact characteristics with other materials such as indiumtin oxide (ITO) and indium zinc oxide (IZO). A good exemplarycombination of the lower film material and the upper film material is Crand Al—Nd alloy. In FIG. 4, the lower and the upper films of the gateelectrodes 123 are indicated by reference numerals 123 p and 123 q,respectively, and the lower and the upper films of the projections 127are indicated by reference numerals 127 p and 127 q, respectively.However, the expansions 125 of the gate lines 121 include only a lowerfilm.

[0070] In addition, the lateral sides of the upper film 121 q and thelower film 121 p are tapered, and the inclination angle of the lateralsides with respect to a surface of the substrate 110 ranges about 30-80degrees.

[0071] A gate insulating layer 140 preferably made of silicon nitride(SiNx) is formed on the gate lines 121 and the gate shorting bar 124.

[0072] A plurality of semiconductor stripes 151 preferably made ofhydrogenated amorphous silicon (abbreviated to “a-Si”) are formed on thegate insulating layer 140. Each semiconductor stripe 151 extendssubstantially in the longitudinal direction and has a plurality ofprojections 154 branched out toward the gate electrodes 123. The widthof each semiconductor stripe 151 becomes large near the gate lines 121such that the semiconductor stripe 151 covers large areas of the gatelines 121.

[0073] A plurality of ohmic contact stripes and islands 161 and 165preferably made of silicide or n+ hydrogenated a-Si heavily doped with ntype impurity are formed on the semiconductor stripes 151. Each ohmiccontact stripe 161 has a plurality of projections 163, and theprojections 163 and the ohmic contact islands 165 are located in pairson the projections 154 of the semiconductor stripes 151.

[0074] The lateral sides of the semiconductor stripes 151 and the ohmiccontacts 161 and 165 are tapered, and the inclination angles thereof arepreferably in a range between about 30-80 degrees.

[0075] A plurality of data lines 171, a plurality of drain electrodes175, a plurality of storage capacitor conductors 177, and a datashorting bar 174 are formed on the ohmic contacts 161 and 165 and thegate insulating layer 140.

[0076] The data lines 171 for transmitting data voltages extendsubstantially in the longitudinal direction and intersect the gate lines121. Each data line 171 includes an expansion 179 having wider width forcontact with another layer or an external device, and an extension 176connected between the expansion 179 and the data shorting bar 174. Mostportions of the data lines 171 as well as the drain electrodes 175 andthe storage capacitor conductors 177 are disposed on the display area,while the expansions 179 and the extensions 176 of the data lines 171 aswell as the data shorting bar 174 are disposed on the peripheral area.

[0077] A plurality of branches of each data line 171, which projecttoward the drain electrodes 175, form a plurality of source electrodes173. Each pair of the source electrodes 173 and the drain electrodes 175are separated from each other and opposite each other with respect to agate electrode 123. A gate electrode 123, a source electrode 173, and adrain electrode 175 along with a projection 154 of a semiconductorstripe 151 form a TFT having a channel formed in the projection 154disposed between the source electrode 173 and the drain electrode 175.

[0078] The storage capacitor conductors 177 overlap the projections 127of the gate lines 121, and the data shorting bar 174 extendssubstantially in the transverse direction.

[0079] The data lines 171, the drain electrodes 175, and the storagecapacitor conductors 177 as well as the data shorting bar 174 alsoinclude a lower film 171 p, 175 p and 177 p preferably made of Mo, Moalloy or Cr and an upper film 171 q, 175 q and 177 q located thereon andpreferably made of Al containing metal or Ag containing metal. However,the expansions 179 of the data lines 171 include only a lower film, andportions of the upper films 175 q and 177 q of the drain electrodes 175and the storage capacitor conductors 177 are removed to expose theunderlying portions of the lower films 175 p and 177 p.

[0080] Like the gate lines 121, the lower film 171 p, 175 p and 177 pand the upper film 171 q, 175 q and 177 q of the data lines 171, thedrain electrodes 175, and the storage capacitor conductors 177 as wellas the data shorting bar 174 have tapered lateral sides, and theinclination angles thereof range about 30-80 degrees.

[0081] The ohmic contacts 161 and 165 are interposed only between theunderlying semiconductor stripes 151 and the overlying data lines 171and the overlying drain electrodes 175 thereon and reduce the contactresistance therebetween. The semiconductor stripes 151 include aplurality of exposed portions, which are not covered with the data lines171 and the drain electrodes 175, such as portions located between thesource electrodes 173 and the drain electrodes 175. Although thesemiconductor stripes 151 are narrower than the data lines 171 at mostplaces, the width of the semiconductor stripes 151 becomes large nearthe gate lines 121 as described above, to smooth the profile of thesurface, thereby preventing the disconnection of the data lines 171.

[0082] A passivation layer 180 is formed on the data lines 171, thedrain electrodes 175, the storage conductors 177, the data shorting bar174, and the exposed portions of the semiconductor stripes 151. Thepassivation layer 180 is preferably made of photosensitive organicmaterial having a good flatness characteristic, low dielectricinsulating material having dielectric constant lower than 4.0 such asa-Si:C:O and a-Si:O:F formed by plasma enhanced chemical vapordeposition (PECVD), or inorganic material such as silicon nitride.

[0083] The passivation layer 180 has a plurality of contact holes 185,187 and 189 exposing the lower films 175 p of the drain electrodes 175,the lower films 177 p of the storage conductors 177, and the expansions179 of the data lines 171, respectively. The passivation layer 180 andthe gate insulating layer 140 have a plurality of contact holes 182exposing the expansions 125 of the gate lines 121. The passivation layer180 and/or the gate insulating layer 140 have a plurality contact holes(not shown) exposing adjacent end portions of the gate shorting bar 124and the data shorting bar 174.

[0084] In addition, FIGS. 3 and 4 shows that the contact holes 182, 185,187 and 189 expose edges of the lower films 125, 175 p, 177 p and 179and some portions of the gate insulating layer 140 and the substrate110. There is no undercut at the contact holes 182, 185, 187 and 189.

[0085] A plurality of pixel electrodes 191, a plurality of contactassistants 192 and 199, and a shorting bar connection 194, which arepreferably made of ITO or IZO, are formed on the passivation layer 180.

[0086] The pixel electrodes 191 are physically and electricallyconnected to the drain electrodes 175 through the contact holes 185 andto the storage capacitor conductors 177 through the contact holes 187such that the pixel electrodes 191 receive the data voltages from thedrain electrodes 175 and transmit the received data voltages to thestorage capacitor conductors 177.

[0087] The pixel electrodes 191 supplied with the data voltages generateelectric fields in cooperation with a common electrode (not shown) onanother panel (not shown), which reorient liquid crystal molecules in aliquid crystal layer (not shown) disposed therebetween.

[0088] A pixel electrode 191 and a common electrode form a liquidcrystal capacitor, which stores applied voltages after turn-off of theTFT. An additional capacitor called a “storage capacitor,” which isconnected in parallel to the liquid crystal capacitor, is provided forenhancing the voltage storing capacity. The storage capacitors areimplemented by overlapping the pixel electrodes 191 with the gate lines121 adjacent thereto (called “previous gate lines”). The capacitances ofthe storage capacitors, i.e., the storage capacitances are increased byproviding the projections 127 at the gate lines 121 for increasingoverlapping areas and by providing the storage capacitor conductors 177,which are connected to the pixel electrodes 191 and overlap theprojections 127, under the pixel electrodes 191 for decreasing thedistance between the terminals.

[0089] The pixel electrodes 191 overlap the gate lines 121 and the datalines 171 to increase aperture ratio but it is optional.

[0090] The contact assistants 192 and 199 are connected to the exposedexpansions 125 of the gate lines 121 and the exposed expansions 179 ofthe data lines 171 through the contact holes 182 and 189, respectively.The contact assistants 192 and 199 are not requisites but preferred toprotect the exposed portions 125 and 179 and to complement theadhesiveness of the exposed portions 125 and 179 and external devices.

[0091] The shorting bar connection 194 is connected to the gate shortingbar 124 and the data shorting bar 174 through the contact holes exposingthem.

[0092] As described above, the lower films 125, 179, 175 p and 177 p ofthe expansions 125 of the gate lines 121, the expansions 179 of the datalines 171, the drain electrodes 175, and the storage capacitorconductors 177, which have a good contact characteristic with ITO andIZO, are exposed, and the contact holes 182, 185, 187 and 189 expose atleast an edge of the lower films 125, 175 p, 177 p and 179. Accordingly,the pixel electrodes 191 and the contact assistants 192 and 199 are incontact with the lower films 175 p, 177 p, 125 and 179 with sufficientlylarge contact areas to provide low contact resistance. Furthermore,since there is no undercut at the contact holes 185, 187 and 189 andthus the pixel electrodes 191 and the contact assistants 199 are also incontact with the gate insulating layer 140 through the contact holes185, 187 and 189, the pixel electrodes 191 and the contact assistants 92and 97 have smooth profiles.

[0093] According to another embodiment of the present invention, thepixel electrodes 191 are made of transparent conductive polymer. For areflective LCD, the pixel electrodes 191 are made of opaque reflectivemetal. In these cases, the contact assistants 192 and 199 may be made ofmaterial such as ITO or IZO different from the pixel electrodes 191.

1st Embodiment Method

[0094] A method of manufacturing the TFT array panel shown in FIGS. 1-4according to an embodiment of the present invention will be nowdescribed in detail with reference to FIGS. 5A to 12 as well as FIGS.1-4.

[0095]FIGS. 5A, 6A, 7A and 9A are layout views of the TFT array panelshown in FIGS. 1-4 in intermediate steps of a manufacturing methodthereof according to an embodiment of the present invention, and FIGS.5B, 6B, 7B and 9B are sectional views of the TFT array panel shown inFIGS. 5A, 6A, 7A and 9A taken along the lines VB-VB′, VIB-VIB′,VIIB-VIIB′, and IXB-IXB′, respectively. FIG. 8 is a sectional view ofthe TFT array panel shown in FIG. 7A taken along the line VIIB-VIIB′ inthe step of the manufacturing method following the step shown in FIG.7B, and FIGS. 11 and 12 are sectional views of the TFT array panel shownin FIG. 9A in the steps of the manufacturing method following the stepshown in FIG. 9B. FIG. 10 illustrates alignment between slits of a maskand a drain electrode.

[0096] Two conductive films, a lower conductive film and an upperconductive film are sputtered in sequence on an insulating substrate 110such as transparent glass. The upper conductive film is preferably madeof Al containing metal such as Al—Nd alloy. An Al—Nd target forsputtering the upper film preferably contains 2 atm % and the upper filmpreferably has a thickness of about 2,500 Å.

[0097] Referring to FIGS. 5A and 5B, the upper conductive film and thelower conductive film are patterned in sequence to form a plurality ofgate lines 121 including a plurality of gate electrodes 123, a pluralityof projections 127, and a gate shorting bar 124.

[0098] Referring to FIGS. 6A and 6B, after sequential deposition of agate insulating layer 140, an intrinsic a-Si layer, and an extrinsica-Si layer, the extrinsic a-Si layer and the intrinsic a-Si layer arephoto-etched to form a plurality of extrinsic semiconductor stripes 164and a plurality of intrinsic semiconductor stripes 151 including aplurality of projections 154 on the gate insulating layer 140. The gateinsulating layer 140 is preferably made of silicon nitride withthickness of about 2,000 Å to about 5,000 Å, and the depositiontemperature is preferably in a range between about 250° C. and about500° C.

[0099] Two conductive films, a lower conductive film and an upperconductive film are sputtered in sequence. The lower conductive film ispreferably made of Mo, Mo alloy or Cr, and preferably has a thickness ofabout 500 Å. It is preferable that the upper conductive film has athickness of about 2,500 Å, the sputtering target for the upperconductive film includes pure Al or Al—Nd containing 2 atomic % Nd, andthe sputtering temperature is about 150° C.

[0100] Referring to FIGS. 7A and 7B, the upper conductive film and thelower conductive film are wet-etched and dry-etched, respectively, orboth the films are wet etched to form a plurality of data lines 171including a plurality of source electrodes 173, a plurality of drainelectrodes 175, a plurality of storage capacitor conductors 177, and adata shorting bar 174. When the lower film is made of Mo or Mo alloy,the upper and the lower layers can be etched under the same etchingconditions.

[0101] Thereafter, portions of the extrinsic semiconductor stripes 164,which are not covered with the data lines 171, the drain electrodes 175,the storage capacitor conductors 177, and the data shorting bar 174, areremoved to complete a plurality of ohmic contact stripes 161 including aplurality of projections 163 and a plurality of ohmic contact islands165 and to expose portions of the intrinsic semiconductor stripes 151.Oxygen plasma treatment preferably follows thereafter in order tostabilize the exposed surfaces of the semiconductor stripes 151.

[0102] As shown in FIG. 8, after depositing a passivation layer 180, aphotoresist film 210 is spin-coated on the passivation layer 180. Thephotoresist film 210 is exposed to light through an exposure mask 300,and developed such that the developed photoresist has a positiondependent thickness as shown in FIG. 9B. The photoresist shown in FIG.9B includes a plurality of first to third portions with decreasedthickness. The first portions in areas A1 and the second portions indata contact areas C1 located on the expansions 179 of the data lines171 and portions of the drain electrodes 175 and the storage capacitorconductors 177 are indicated by reference numerals 212 and 214,respectively, and no reference numeral is assigned to the third portionsin gate contact areas B1 located on the expansions 125 of the gate lines121 since they have substantially zero thickness to expose underlyingportions of the passivation layer 180. The portions 214 located on theexpansions 125 of the gate lines 121 may have the same thickness as thethird portions. Furthermore, the second portions 214 of the photoresistare disposed on a portion of the data shorting bar 174, and the thirdportions or the second portions 214 of the photoresist are disposed on aportion of the gate shorting bar 124. The thickness ratio of the secondportions 214 to the first portions 212 is adjusted depending upon theprocess conditions in the subsequent process steps.

[0103] The position-dependent thickness of the photoresist is obtainedby several techniques, for example, by providing translucent areas onthe exposure mask 300 as well as transparent areas and light blockingopaque areas. The translucent areas may have a slit pattern, a latticepattern, a thin film(s) with intermediate transmittance or intermediatethickness. When using a slit pattern, it is preferable that the width ofthe slits or the distance between the slits is smaller than theresolution of a light exposer used for the photolithography. Anotherexample is to use reflowable photoresist. In detail, once a photoresistpattern made of a reflowable material is formed by using a normalexposure mask only with transparent areas and opaque areas, it issubject to reflow process to flow onto areas without the photoresist,thereby forming thin portions.

[0104] Referring to FIG. 10, the exposure mask 300 according thisembodiment has a plurality of slits 310 for forming the second portions214 of the photoresist. The slits 310 are approximately rectilinear andthey have depressions (or projections). The slits 310 extendsubstantially parallel to each other and they are arranged in theirwidth direction. Each slit 310 has a width in a range of about 0.8-2.0microns since a slit wider than 2.0 microns may serve as a transparentarea. An exposure mask having a slit pattern is easily manufactured withcheap cost and it has a uniform reproductivity.

[0105] When aligning the exposure mask 300 with the substrate 110, theslits 310 for the drain electrode 175 are arranged such that theirlength is substantially parallel to an edge of the drain electrode 175,at least two slits 310 are disposed out of the drain electrode 175, aslit 310 overlaps an edge of the drain electrode 175, and thedepressions of the slits 310 overlap edges of the drain electrode 175.The slits 310 for other elements such as the storage capacitorconductors 177, the expansions 179 and shorting bars 124 and 174 arealigned in a similar manner. The width and the distance of the slits 310for the drain electrodes 175 and the storage capacitor conductors 177 inthe display area is preferably different from those for the expansions179 and the shorting bars 124 and 174 in the peripheral area. Althoughthe above-described alignment is advantageous for obtaining alignmentmargin of the exposure mask and thickness margin of the second portions214 of the photoresist and for obtaining uniform thickness of the secondportions 214 of the photoresist, there may be other ways of thealignment between the slits 310 and the related elements 175, 177 and179.

[0106] The different thickness of the photoresist 212 and 214 enables toselectively etch the underlying layers when using suitable processconditions. Therefore, a plurality of contact holes 182, 185, 187 and189 are obtained. The second portions 214 may be disposed on any contactholes and they prevent the gate insulating layer 140 at the contactholes 185, 187 and 189 exposing the drain electrodes 175, the storagecapacitor electrodes 177, and the expansions 179 of the data lines 171from being etched, thereby preventing undercut at the contact holes 185,187 and 189.

[0107] For descriptive purpose, portions on the areas A1 are calledfirst portions, portions of the passivation layer 180, the drainelectrodes 175, the storage capacitor conductors 177, the data lines171, and the gate insulating layer 140 on the data contact areas C1 arecalled second portions, and portions of the passivation layer 180, thegate insulating layer 140, and the gate lines 121 on the gate contactareas B1 are called third portions.

[0108] An exemplary sequence of forming such a structure is as follows:

[0109] As shown in FIG. 11, the exposed third portions of thepassivation layer 180 on the gate contact areas B1 are removed by dryetching, preferably under the condition that the etching ratios for thepassivation layer 180 and the photoresist 212 and 214 are substantiallyequal such that the second portions 214 of the photoresist can be alsoremoved or can be remained with reduced thickness for next etching step.Although the dry etching may etch out the top portions of the secondportions of the passivation layer 180 and the third portions of the gateinsulating layer 140, it is preferable that the thickness of the thirdportions of the gate insulating layer 140 is smaller than that of thesecond portions of the passivation layer 180 so that the second portionsof the gate insulating layer 140 may not be removed in later steps andthus the undercut can be prevented. Residue of the second portions 214of the photoresist remained on the data contact areas C1 is removed byashing to completely expose the second portions of the passivation layer180.

[0110] Referring to FIG. 12, the third portions of the gate insulatinglayer 140 and the second portions of the passivation layer 180 areremoved to complete the contact holes 182, 185, 187 and 189. The removalof those portions are made by dry etching under the condition that theetching ratios for the gate insulating layer 140 and the passivationlayer 180 are substantially equal.

[0111] Subsequently, the third portions of the upper film 125 q of theexpansions 125 of the gate lines 121 and the second portions of theupper films 175 q, 177 q and 179 q of the drain electrodes 175, thestorage capacitor conductors 177, and the expansions 179 of the datalines 171 are removed to expose the underlying lower films 125 p, 175 q,177 p and 179 p.

[0112] Finally, as shown in FIGS. 1-4, a plurality of pixel electrodes191, a plurality of contact assistants 192 and 199, and a shorting barconnection 194 are formed on the passivation layer 180 by sputtering andphoto-etching an ITO or IZO layer. Since there is no undercut under thedrain electrodes 175, the storage capacitor conductors 177, and theexpansions 125 and 179, the profiles of the pixel electrodes 179 and thecontact assistants 192 and 199 become smooth. In addition, since thepixel electrodes 191 and the contact assistants 192 and 199 are incontact with the lower films 175 p and 177 p of the drain electrodes 175and the storage capacitor conductors 177 and the lower films 125 and 179of the gate lines 121 and the data lines 171, which have good contactcharacteristics with ITO and IZO, the contact resistance at contactportions is reduced.

[0113] In the TFT array panel according to an embodiment of the presentinvention, the gate lines 121 and the data lines 171 include Al or Alalloy with low resistivity while they have minimized contact resistancebetween the pixel electrodes 191 and the contact assistants 192 and 199.In addition, the smooth profile of the contact assistants 192 and 199increases the reliability of the contact between the contact assistants192 and 199 and external driving integrated circuit chips.

2nd Embodiment Structure

[0114] A TFT array panel for an LCD according to another embodiment ofthe present invention will be described in detail with reference toFIGS. 13-15.

[0115]FIG. 13 is a layout view of an exemplary TFT array panel for anLCD according to another embodiment of the present invention, and FIGS.14 and 15 are sectional views of the TFT array panel shown in FIG. 13taken along the line XIV-XIV′ and the line XV-XV′, respectively.

[0116] For simplicity, the extensions 126 and 176 shown in FIG. 3 areomitted.

[0117] As shown in FIGS. 13-15, a layered structure of a TFT array panelof an LCD according to this embodiment is almost the same as that shownin FIGS. 3 and 4. That is, a plurality of gate lines 121 including aplurality of gate electrodes 123 are formed on a substrate 110, and agate insulating layer 140, a plurality of semiconductor stripes 151including a plurality of projections 154, and a plurality of ohmiccontact stripes 161 including a plurality of projections 163 and aplurality of ohmic contact islands 165 are sequentially formed thereon.A plurality of data lines 171 including a plurality of source electrodes173 and a plurality of drain electrodes 175 are formed on the ohmiccontacts 161 and 165, and a passivation layer 180 is formed thereon. Aplurality of contact holes 182, 185 and 189 are provided at thepassivation layer 180 and/or the gate insulating layer 140, and aplurality of pixel electrodes 191 and a plurality of contact assistants192 and 199 are formed on the passivation layer 180.

[0118] Different from the TFT array panel shown in FIGS. 3 and 4, theTFT array panel according to this embodiment provides a plurality ofstorage electrode lines 131, which are separated from the gate lines121, on the same layer as the gate lines 121 without projections. Thestorage electrode lines 131 include, like the gate lines 121, a lowerfilm 131 p and an upper film 131 q. The storage electrode lines 131 aresupplied with a predetermined voltage such as the common voltage.Without providing the storage capacitor conductors 177 shown in FIGS. 3and 4, the drain electrodes 175 extend to overlap the storage electrodelines 131 to form storage capacitors. The storage electrode lines 131may be omitted if the storage capacitance generated by the overlappingof the gate lines 121 and the pixel electrodes 191 is sufficient.

[0119] Furthermore, the contact holes 182 and 189 exposes portions ofexpansions 125 and 179 of the gate lines 121 and the data lines 175instead of exposing all portions of the expansions 125 and 179 such thatsome portions of a upper film 125 q and 179 q are remained.

[0120] The semiconductor stripes 151 have almost the same planar shapesas the data lines 171 and the drain electrodes 175 as well as theunderlying ohmic contacts 161 and 165, except for the projections 154where TFTs are provided. That is, the semiconductor stripes 151 includesome exposed portions, which are not covered with the data lines 171 andthe drain electrodes 175, such as portions located between the sourceelectrodes 173 and the drain electrodes 175.

2nd Embodiment Method

[0121] Now, a method of manufacturing the TFT array panel shown in FIGS.13-15 according to an embodiment of the present invention will bedescribed in detail with reference to FIGS. 16A-25B as well as FIGS.13-15.

[0122]FIG. 16A is a layout view of a TFT array panel shown in FIGS.13-15 in the first step of a manufacturing method thereof according toan embodiment of the present invention; FIGS. 16B and 16C are sectionalviews of the TFT array panel shown in FIG. 16A taken along the linesXVIB-XVIB′ and XVIC-XVIC′, respectively; FIGS. 17A and 17B are sectionalviews of the TFT array panel shown in FIG. 16A taken along the linesXVIB-XVIB′ and XVIC-XVIC′, respectively, and illustrate the stepfollowing the step shown in FIGS. 16B and 16C; FIG. 18A is a layout viewof the TFT array panel in the step following the step shown in FIGS. 17Aand 17B; FIGS. 18B and 18C are sectional views of the TFT array panelshown in FIG. 18A taken along the lines XVIIIB-XVIIIB′ andXVIIIC-XVIIIC′, respectively; FIGS. 19A, 20A and 21A and FIGS. 19B, 20Band 21B are respective sectional views of the TFT array panel shown inFIG. 18A taken along the lines XVIIIB-XVIIIB′ and XVIIIC-XVIIIC′,respectively, and illustrate the steps following the step shown in FIGS.18B and 18C; FIG. 22A is a layout view of a TFT array panel in the stepfollowing the step shown in FIGS. 21A and 21B; FIGS. 22B and 22C aresectional views of the TFT array panel shown in FIG. 22A taken along thelines XXIIB-XXIIB′ and XXIIC-XXIIC′, respectively; and FIGS. 23A, 24Aand 25A and FIGS. 23B, 24B and 25B are respective sectional views of theTFT array panel shown in FIG. 22A taken along the lines XXIIB-XXIIB′ andXXIIC-XXIIC′, respectively, and illustrate the steps following the stepshown in FIGS. 22B and 22C.

[0123] Referring to FIGS. 16A-16C, a plurality of gate lines 121including a plurality of gate electrodes 123, a plurality of storageelectrode lines 131, and a gate shorting bar 124 are formed on asubstrate 110 by photo etching. The gate lines 121 and the storageelectrode lines 131 as well as the gate shorting bar 124 include lowerfilms 121 p and 131 p and the upper films 121 q and 131 q.

[0124] As shown in FIGS. 17A and 17B, a gate insulating layer 140, anintrinsic a-Si layer 150, and an extrinsic a-Si layer 160 aresequentially deposited by CVD such that the layers 140, 150 and 160 bearthickness of about 1,500-5,000 Å, about 500-2,000 Å and about 300-600 Å,respectively. A conductive layer 170 including a lower film 170 p and anupper film 170 q having a thickness of about 1,500-3,000 Å is depositedby sputtering, and a photoresist film 310 with the thickness of about1-2 microns is coated on the conductive layer 170.

[0125] The photoresist film 310 is exposed to light through an exposuremask (not shown), and developed such that the developed photoresist hasa position dependent thickness. The photoresist shown in FIGS. 18B and18C includes a plurality of first to third portions with decreasedthickness. The first portions located on wire areas A2 and the secondportions located on channel areas C2 are indicated by reference numerals312 and 314, respectively, and no reference numeral is assigned to thethird portions located on remaining areas B2 since they havesubstantially zero thickness to expose underlying portions of theconductive layer 170.

[0126] The different thickness of the photoresist 312 and 314 enables toselectively etch the underlying layers when using suitable processconditions. Therefore, a plurality of data lines 171 including aplurality of source electrodes 173, a plurality of drain electrodes 175,and a data shorting bar 174 as well as a plurality of ohmic contactstripes 161 including a plurality of projections 163, a plurality ofohmic contact islands 165 and a plurality of semiconductor stripes 151including a plurality of projections 154 are obtained by a series ofetching steps.

[0127] For descriptive purpose, portions of the conductive layer 170,the extrinsic a-Si layer 160, and the intrinsic a-Si layer 150 on thewire areas A2 are called first portions, portions of the conductivelayer 170, the extrinsic a-Si layer 160, and the intrinsic a-Si layer150 on the channel areas C2 are called second portions, and portions ofthe conductive layer 170, the extrinsic a-Si layer 160, and theintrinsic a-Si layer 150 on the remaining areas B2 are called thirdportions.

[0128] An exemplary sequence of forming such a structure is as follows:

[0129] (1) Removal of third portions of the conductive layer 170, theextrinsic a-Si layer 160 and the intrinsic a-Si layer 150 on the wireareas A2;

[0130] (2) Removal of the second portions 314 of the photoresist;

[0131] (3) Removal of the second portions of the conductive layer 170and the extrinsic a-Si layer 160 on the channel areas C2; and

[0132] (4) Removal of the first portions 312 of the photoresist.

[0133] Another exemplary sequence is as follows:

[0134] (1) Removal of the third portions of the conductive layer 170;

[0135] (2) Removal of the second portions 314 of the photoresist;

[0136] (3) Removal of the third portions of the extrinsic a-Si layer 160and the intrinsic a-Si layer 150;

[0137] (4) Removal of the second portions of the conductive layer 170;

[0138] (5) Removal of the first portions 312 of the photoresist; and

[0139] (6) Removal of the second portions of the extrinsic a-Si layer160.

[0140] The first example is described in detail.

[0141] As shown in FIGS. 19A and 19B, the exposed third portions of theconductive layer 170 on the remaining areas B2 are removed by wetetching or dry etching to expose the underlying third portions of theextrinsic a-Si layer 160. A Mo, MoW, Al, Ta or Ta film can be etched byany of dry etching and wet etching, while a Cr film is hardly etched bydry etching. When the lower film 170 p is made of Cr, wet etching withan etchant of CeNHO₃ can be used. When the lower film 170 p is Mo orMoW, a gas mixture of CF₄ and HCl or a gas mixture of CF₄ and O2 can beused and the latter gas mixture etches the photoresist by an etchingratio similar to that of the conductive film.

[0142] Reference numeral 178 indicates portions of the conductive layer170 including the data lines 171 and the drain electrode 175 connectedto each other. The dry etching may etch out the top portions of thephotoresist 312 and 314.

[0143] Referring to FIGS. 20A and 20B, the third portions of theextrinsic a-Si layer 160 on the areas B2 and of the intrinsic a-Si layer150 are removed preferably by dry etching and the second portions 314 ofthe photoresist are removed to expose the second portions of theconductors 178. The removal of the second portions 314 of thephotoresist are performed either simultaneously with or independent fromthe removal of the third portions of the extrinsic a-Si layer 160 and ofthe intrinsic a-Si layer 150. A gas mixture of SF₆ and HCl or a gasmixture of SF₆ and O₂ can etch the a-Si layers 150 and 160 and thephotoresist by nearly the same etching ratio. Residue of the secondportions 314 of the photoresist remained on the channel areas C2 isremoved by ashing.

[0144] The semiconductor stripes 151 are completed in this step, andreference numeral 164 indicates portions of the extrinsic a-Si layer 160including the ohmic contact stripes and islands 161 and 165 connected toeach other, which are called “extrinsic semiconductor stripes.”

[0145] As shown in FIGS. 21A and 21B, the second portions of theconductors 178 and the extrinsic a-Si stripes 164 on the channel areasC2 as well as the first portion 312 of the photoresist are removed.

[0146] Both the conductors 178 and the extrinsic semiconductor stripes164 may be dry etched with a gas mixture of SF₆ and O₂.

[0147] Alternatively, the conductors 178 are dry etched, while theextrinsic semiconductor stripes 164 are dry etched. Since lateral sidesof the conductors 178 are also dry etched, while lateral sides of theextrinsic semiconductor stripes 164 are hardly etched, step-wise lateralprofiles are obtained. Examples of the gas mixtures are CF₄ and HCl andCF₄ and O₂, as described above. The latter gas mixture leaves uniformthickness of the intrinsic semiconductor stripes 151.

[0148] As shown in FIG. 21B, top portions of the projections 154 of theintrinsic semiconductor stripes 151 on the channel areas C2 may beremoved to cause thickness reduction, and the first portions 312 of thephotoresist are etched to a predetermined thickness.

[0149] In this way, each conductor 178 is divided into a data line 171and a plurality of drain electrodes 175 to be completed, and eachextrinsic semiconductor stripe 164 is divided into an ohmic contactstripe 161 and a plurality of ohmic contact islands 165 to be completed.

[0150] As shown in FIGS. 22A-22C, after depositing a passivation layer180, a photoresist film is spin-coated on the passivation layer 180. Thephotoresist film is exposed to light through an exposure mask (notshown), and developed such that the developed photoresist has a positiondependent thickness. The photoresist shown in FIGS. 22B and 22C includesa plurality of first to third portions with decreased thickness. Thefirst portions in areas A3 and the second portions in data contact areasC3 located on the expansions 179 of the data lines 171 and portions ofthe drain electrodes 175 are indicated by reference numerals 412 and414, respectively, and no reference numeral is assigned to the thirdportions in gate contact areas B3 located on the expansions 125 of thegate lines 121 since they have substantially zero thickness to exposeunderlying portions of the passivation layer 180. The thickness ratio ofthe second portions 414 to the first portions 412 is adjusted dependingupon the process conditions in the subsequent process steps.

[0151] The different thickness of the photoresist 412 and 414 enables toselectively etch the underlying layers when using suitable processconditions. Therefore, a plurality of contact holes 182, 185, 187 and189 are obtained.

[0152] For descriptive purpose, portions on the areas A3 are calledfirst portions, portions of the passivation layer 180, the drainelectrodes 175, the data lines 171, and the gate insulating layer 140 onthe data contact areas C3 are called second portions, and portions ofthe passivation layer 180, the gate insulating layer 140, and the gatelines 121 on the gate contact areas B3 are called third portions.

[0153] An exemplary sequence of forming such a structure is as follows:

[0154] As shown in FIGS. 23A and 23B, the exposed third portions of thepassivation layer 180 on the gate contact areas B3 are removed byetching. Although the dry etching may etch out the top portions of thesecond portions of the passivation layer 180 and the third portions ofthe gate insulating layer 140, it is preferable that the third portionsof the gate insulating layer 140 is thinner than the second portions ofthe passivation layer 180 so that the second portions of the gateinsulating layer 140 may not be removed in later steps. Residue of thesecond portions 414 of the photoresist remained on the data contactareas C3 is removed by ashing to completely expose the second portionsof the passivation layer 180.

[0155] Referring to FIGS. 24A and 24B, the third portions of the gateinsulating layer 140 and the second portions of the passivation layer180 are removed to complete the contact holes 182, 185 and 189. Theremoval of those portions are made by dry etching under the conditionthat the etching ratios for the gate insulating layer 140 and thepassivation layer 180 are substantially equal. Since the thickness ofthe third portions of the gate insulating layer 140 is smaller than thatof the second portions of the passivation layer 180, the third portionsof the gate insulating layer 140 and the second portions of thepassivation insulating layer 180 are completely removed, andsimultaneously, the second portions of the gate insulating layer 140 areremained to prevent the undercut of the gate insulating layer 140 underthe drain electrodes 175.

[0156] As shown in FIGS. 25A and 25B, after removing the photoresist 412and 414, the third portions of the upper film 125 q of the expansions125 of the gate lines 121 and the second portions of the upper films 175q and 179 q of the drain electrodes 175, and the expansions 179 of thedata lines 171 are removed to expose the underlying lower films 125 p,175 p and 179 p.

[0157] Finally, as shown in FIGS. 13 to 15, an ITO or IZO layer with athickness in a range between about 500 Å and about 1,500 Å is sputteredand photo-etched to form a plurality of pixel electrodes 191, aplurality of contact assistants 192 and 199, and a shorting barconnection 194. The etching of the IZO layer preferably includes wetetching using a Cr etchant of HNO₃/(NH₄)₂Ce(NO₃)₆/H₂O, which does noterode Al of the data lines 171 and the drain electrodes 175.

[0158] This embodiment simplifies the manufacturing process by formingthe data lines 171 and the drain electrodes 175 as well as the ohmiccontacts 161 and 165 and the semiconductor stripes 151 and using asingle photolithography step.

3rd Embodiment Structure

[0159] A TFT array panel for an LCD according to another embodiment ofthe present invention will be described in detail with reference toFIGS. 26 and 27.

[0160]FIG. 26 is a layout view of an exemplary TFT array panel for anLCD according to another embodiment of the present invention, and FIG.27 is a sectional view of the TFT array panel shown in FIG. 26 takenalong the line XXVII-XXVII′.

[0161] As shown in FIGS. 26 and 27, a layered structure of a TFT arraypanel of an LCD according to this embodiment is almost the same as thatshown in FIGS. 3 and 4. That is, a plurality of gate lines 121 includinga plurality of gate electrodes 123 are formed on a substrate 110, and agate insulating layer 140, a plurality of semiconductor stripes 151including a plurality of projections 154, and a plurality of ohmiccontact stripes 161 including a plurality of projections 163 and aplurality of ohmic contact islands 165 are sequentially formed thereon.A plurality of data lines 171 including a plurality of source electrodes173 and a plurality of drain electrodes 175 are formed on the ohmiccontacts 161 and 165, and a passivation layer 180 is formed thereon. Aplurality of contact holes 182 and 189 exposing expansions 125 and 179of the gate lines 121 and the data lines 171 are provided at thepassivation layer 180 and/or the gate insulating layer 140, and aplurality of pixel electrodes 191 and a plurality of contact assistants192 and 199 are formed.

[0162] Different from the TFT array panel shown in FIGS. 3 and 4, thepassivation layer 180 of the TFT array panel according to thisembodiment includes a plurality of portions extending along the datalines 171 and a plurality of portions disposed near the expansions 125of the gate lines 121. The passivation layer 180 covers the data lines171 including the source electrodes 173 and portions of the drainelectrodes 175, while other portions of the drain electrodes 175 and thestorage capacitor conductors 177 are not covered with the passivationlayer 180.

[0163] In addition, as well as the semiconductor stripes 151 and theohmic contacts 161 and 165, a plurality of semiconductor islands 157 anda plurality of ohmic contacts 167 thereover are provided between thestorage conductors 177 and the gate insulating layer 140.

[0164] The semiconductor stripes and islands 151 and 157 have almost thesame planar shapes as the passivation layer 180 except for portionsunder the exposed portions of the drain electrodes 175, the expansions125 of the gate lines 121, expansions 179 of the data lines 171, and thestorage capacitor conductors 177. In particular, the semiconductorislands 157, the ohmic contact islands 167 and the storage conductors177 have substantially the same planar shape. In addition, the ohmiccontact stripes and islands 161 and 165 have substantially the sameplanar shape as the data lines 171 and the drain electrodes 175. Thesemiconductor stripes 151 and the passivation layer 180 has a pluralityof trenches T exposing the gate insulating layer 140 and surroundingexpansions 125 and 179 of the gate lines 121 and the data lines 171 forseparating the semiconductors 151.

[0165] Most portions of the pixel electrodes 191 are disposed directlyon the gate insulating layer 140 and some portions of the pixelelectrodes 191 are disposed directly on the exposed portions of thedrain electrodes 175 and portions of the storage capacitor conductors177 for electrical connection to the drain electrodes 175 and thestorage capacitor conductors 177.

3rd Embodiment Method

[0166] Now, a method of manufacturing the TFT array panel shown in FIGS.26 and 27 according to an embodiment of the present invention will bedescribed in detail with reference to FIGS. 28A-32 as well as FIGS. 26and 27.

[0167]FIGS. 28A, 29A and 30A are layout views of the TFT array panelshown in FIGS. 26 and 27 in intermediate steps of a manufacturing methodthereof according to an embodiment of the present invention, and FIGS.28B, 29B and 30B are sectional views of the TFT array panel shown inFIGS. 28A, 29A and 30A taken along the lines XXVIIIB-XXVIIIB′,XXIXB-XXIXB′, and XXX-XXX′, respectively. FIGS. 31 and 32 are sectionalviews of the TFT array panel shown in FIG. 30A taken along the lineXXXB-XXXB′ in the steps of the manufacturing method following the stepshown in FIG. 30B.

[0168] Referring to FIGS. 28A and 28B, a conductive layer having athickness of about 1,000-3,000 Å is deposited on a substrate 110preferably by sputtering and dry or wet etched to form a plurality ofgate lines 121 including a plurality of gate electrodes 123 and a gateshorting bar 124.

[0169] As shown in FIGS. 29A and 29B, a gate insulating layer 140, anintrinsic a-Si layer 150, and an extrinsic a-Si layer 160 aresequentially deposited by CVD such that the layers 140, 150 and 160 bearthickness of about 1,500-5,000 Å, about 500-1,500 Å and about 300-600 Å,respectively. A conductive layer 170 including a lower film 170 p and anupper film 170 q having a thickness of about 1,500-3,000 Å is depositedpreferably by sputtering and the conductive layer 170 and the extrinsica-Si layer 160 are patterned to form a plurality of data lines 171including a plurality of source electrodes 173, a plurality of drainelectrodes, a plurality of storage capacitor conductors 177, and a datashorting bar 174 as well as a plurality of ohmic contacts 161, 165 and167.

[0170] As shown in FIGS. 30A and 30B, after depositing a passivationlayer 180 having thickness equal to or larger than about 3,000 Å by CVDof silicon nitride or spin-coating of organic insulator, a photoresistfilm is spin-coated on the passivation layer 180. The photoresist filmis exposed to light through an exposure mask (not shown), and developedsuch that the developed photoresist has a position dependent thickness.The photoresist shown in FIGS. 30B includes a plurality of first tothird portions with decreased thickness. The first portions in firstareas A4 and the second portions in second areas C4 located on theexpansions 179 of the data lines 171 and portions of the drainelectrodes 175 are indicated by reference numerals 512 and 514,respectively, and no reference numeral is assigned to the third portionsin third areas B4 located on the expansions 125 of the gate lines 121since they have substantially zero thickness to expose underlyingportions of the passivation layer 180. The thickness ratio of the secondportions 514 to the first portions 512 is adjusted depending upon theprocess conditions in the subsequent process steps. Portions (not shown)of the photoresist disposed on areas other than the display area and theperipheral area, which are located on portions of the intrinsic s-Silayer 150 to be removed, may have a thickness different from the secondportions 514, which can be made by changing width of slits and distancebetween the slits in an exposure mask.

[0171] The different thickness of the photoresist 512 and 514 enables toselectively etch the underlying layers when using suitable processconditions. Therefore, the passivation layer 180 having a plurality ofcontact holes 182 and 189 and a plurality of trenches T and a pluralityof semiconductor stripes and islands 151 and 157 are obtained.

[0172] For descriptive purpose, portions on the areas A4 are calledfirst portions, portions of the passivation layer 180, the drainelectrodes 175, the data lines 171, the intrinsic a-Si layer 150, andthe gate insulating layer 140 on the second areas C4 are called secondportions, and portions of the passivation layer 180, the intrinsic a-Silayer 150, the gate insulating layer 140, and the gate lines 121 on thethird areas B2 are called third portions.

[0173] An exemplary sequence of forming such a structure is as follows:

[0174] As shown in FIG. 31, the exposed third portions of thepassivation layer 180 and the intrinsic a-Si layer 150 on the thirdareas B4 are removed by dry etching preferably using a gas mixture ofSF₆ and N₂ or SF₆ and HCl and simultaneously, the second portions 514and the first portions 512 of the photoresist is etched. Although thethird portions of the gate insulating layer 140 may be also removed, itis preferable that the second portions of the passivation layer 180 arenot exposed by controlling the consuming amount of the photoresist.

[0175] The second portions 514 of the photoresist remained on the secondareas C4 is removed by ashing preferably using a gas mixture of N₆ andO₂ or Ar and O₂ to completely expose the second portions of thepassivation layer 180.

[0176] Referring to FIG. 32, the third portions of the gate insulatinglayer 140 and the second portions of the passivation layer 180 areremoved to expose the third portions of the gate lines 121, the storagecapacitor conductors 177, the second portions of the drain electrodes175, the data lines 171, and the intrinsic a-Si layer 150 by etchingunder the condition that the etching selectivity for the gate insulatinglayer 140 and the passivation layer 180 with respect to the intrinsica-Si layer 150 is excellent. Thereafter, the exposed second portions ofthe intrinsic a-Si layer 150 is removed by etching preferably using agas mixture of Cl₂ and O₂ or SF₆, HCl, O₂ and Ar to complete thesemiconductor stripes and islands 171 and 177 and the trenches T.

[0177] After removing the photoresist 512 and 514, the third portions ofthe upper film 125 q of the expansions 125 of the gate lines 121 and thesecond portions of the upper films 175 q, 177 q and 179 q of the drainelectrodes 175, the storage capacitor conductors 177, and the expansions179 of the data lines 171 are removed to expose the underlying lowerfilms 125 p, 175 p, 177 p and 179 p.

[0178] Finally, as shown in FIGS. 26 and 27, an ITO or IZO layer with athickness in a range between about 400 Å and about 500 Å is sputteredand photo-etched to form a plurality of pixel electrodes 191, aplurality of contact assistants 192 and 199, and a shorting barconnection 194.

4th Embodiment Structure

[0179] A TFT array panel for an LCD according to another embodiment ofthe present invention will be described in detail with reference toFIGS. 33 and 34.

[0180]FIG. 33 is a layout view of an exemplary TFT array panel for anLCD according to another embodiment of the present invention, and FIG.34 is a sectional view of the TFT array panel shown in FIG. 33 takenalong the line XXXIV-XXXIV′.

[0181] For simplicity, the extensions 126 and 176 shown in FIG. 3 areomitted.

[0182] As shown in FIGS. 33 and 34, a layered structure of a TFT arraypanel of an LCD according to this embodiment is almost the same as thatshown in FIGS. 3 and 4. That is, a plurality of gate lines 121 includinga plurality of gate electrodes 123 and a plurality of projections 127are formed on a substrate 110, and a gate insulating layer 140, aplurality of semiconductor stripes 151 including a plurality ofprojections 154, and a plurality of ohmic contact stripes 161 includinga plurality of projections 163 and a plurality of ohmic contact islands165 are sequentially formed thereon. A plurality of data lines 171including a plurality of source electrodes 173, a plurality of drainelectrodes 175, and a plurality of storage capacitor conductors 177 areformed on the ohmic contacts 161 and 165 and the gate insulating layer140, and a passivation layer 180 is formed thereon. A plurality ofcontact holes 182, 185, 187 and 189 are provided at the passivationlayer 180 and/or the gate insulating layer 140, and a plurality of pixelelectrodes 191 and a plurality of contact assistants 192 and 199 areformed on the passivation layer 180.

[0183] Different from the TFT array panel shown in FIGS. 3 and 4, aplurality of red, green and blue color filters R, G and B are formedunder the passivation layer 180. The color filters R, G and B has aplurality of openings C1 and C2 exposing the drain electrodes 175 andthe storage capacitor conductors 177. The color filters R, G and Boverlap each other to prevent light leakage and the contact holes 185and 187 are disposed within the openings C1 and C2. Alternatively, theopenings C1 and C2 and the contact holes 185 and 187 may have step-widesidewalls.

[0184] Furthermore, the contact holes 182 and 189 exposes portions ofexpansions 125 and 179 of the gate lines 121 and the data lines 175instead of exposing all portions of the expansions 125 and 179 such thatsome portions of a upper film 125 q and 179 q are remained.

[0185] Summary

[0186] As described above, the edges of the drain electrodes are exposedwith remaining the gate insulating layer under the drain electrodes toprevent the undercut at the signal lines and to smoothing the profilesof the contact portions such that the disconnection of the pixelelectrodes is prevented. In addition, the lower film having low contactresistance is exposed to secure the reliability of the contact portions.Furthermore, the upper film having low resistivity is included toimprove the quality of the product. Moreover, the manufacturing methodis simplified.

[0187] While the present invention has been described in detail withreference to the preferred embodiments, those skilled in the art willappreciate that various modifications and substitutions can be madethereto without departing from the spirit and scope of the presentinvention as set forth in the appended claims.

What is claimed is:
 1. A thin film transistor array panel comprising: agate line formed on an insulating substrate; a gate insulating layer onthe gate line; a semiconductor layer on the gate insulating layer; adata line formed on the gate insulating layer and including a portiondisposed on the semiconductor layer; a passivation layer formed on thedata line and having a first contact hole exposing at least a portion ofa boundary of the gate line or the data line; and a contact assistantformed on the passivation layer and on the exposed portion of theboundary of the gate line or the data line.
 2. The thin film transistorarray panel of claim 1, wherein at least one of the gate line, the dataline, and the drain electrode comprises a lower film of Cr, Mo or Moalloy and an upper film of Al or Al alloy.
 3. The thin film transistorarray panel of claim 2, wherein the contact assistant is in contact withthe lower film.
 4. The thin film transistor array panel of claim 4,wherein the contact assistant comprises ITO or IZO.
 5. The thin filmtransistor array panel of claim 5, further comprising: a drain electrodeseparated from the data line and formed on the gate insulating layer andthe semiconductor layer; and a pixel electrode formed on the passivationlayer and connected to the drain electrode through a second contacthole.
 6. An exposure mask comprising: an opaque area blocking light; anda slit pattern formed in the opaque area and including a plurality ofslits, wherein the slits are substantially rectilinear, and width ofeach slit and distance between the slits are in a range about 0.8-2.0microns.
 7. The mask of claim 6, wherein the slits have depressions. 8.The mask of claim 6, wherein the mask is utilized in manufacturing athin film transistor panel including a display area where a plurality ofsignal lines intersect each other and a peripheral area where endportions of the signal lines are disposed, the slits include first slitsin the display area and second slits in the peripheral area, and thefirst and the second slits have different width and distance.
 9. Themask of claim 6, wherein the mask is utilized in manufacturing a thinfilm transistor panel including a display area where images aredisplayed and a peripheral area around the display area, the slitsinclude first slits in the display area and in the peripheral area andsecond slits in a remaining area, and the first and the second slitshave different width and distance.
 10. A method of manufacturing a thinfilm transistor array panel, the method comprising: forming a gate lineon an insulating substrate; forming a gate insulating layer; forming asemiconductor member; forming a data conductive layer including a dataline and a drain electrode; forming a passivation layer having a contacthole exposing at least a portion of the drain electrode and a portion ofthe gate insulating layer near an edge of the drain electrode; andforming a pixel electrode connected to the drain electrode through thecontact hole, wherein at least one of the semiconductor member and thepassivation layer is patterned by photolithography using a mask having aplurality of substantially rectilinear slits and width of each slit anddistance between the slits range from about 0.8 to about 2.0 microns.11. The method of claim 10, wherein the mask comprises a first areablocking light, a second area provided with the slits for partiallytransmitting light, and a third area fully transmitting light.
 12. Themethod of claim 11, wherein the photolithography forms a positivephotoresist including a first portion on the data line and a firstportion of the drain electrode, a second portion on a second portion ofthe drain electrode, and a third portion on an end portion of the gateline, the second portion of the photoresist is thinner than the firstportion of the photoresist, and the third portion of the photoresist isthinner than the second portions of the photoresist.
 13. The method ofclaim 12, wherein the photoresist further comprises a fourth portion onan end portion of the data line and having a thickness smaller than thefirst portion of the photoresist.
 14. The method of claim 13, furthercomprising: performing etching using the photoresist to expose portionsof the passivation layer under the second and the fourth portions of thephotoresist and a portion of the gate insulating layer under the thirdportion; and removing the exposed portions of the passivation layer andthe gate insulating layer to form contact holes exposing the endportions of the gate line and the data line.
 15. The method of claim 14,wherein the slits include first slits corresponding to the secondportion of the photoresist and second slits corresponding to the fourthportion of the photoresist, and the first and the second slits havedifferent width and distance.
 16. The method of claim 13, wherein thepatterning of at least one of the semiconductor member and thepassivation layer by photolithography comprises: depositing asemiconductor layer on the gate insulating layer; depositing aninsulating layer on the data conductive layer; forming the photoresiston the insulating layer; performing etching using the photoresist toexpose portions of the passivation layer under the second and the fourthportions of the photoresist and a portion of the gate insulating layerunder the third portion; removing the exposed portions of thepassivation layer and the gate insulating layer to form contact holesexposing the end portions of the gate line and the data line and toexpose portions of the semiconductor layer; and removing the exposedportions of the semiconductor layer to form the semiconductor member.17. The method of claim 16, wherein the semiconductor member comprises aplurality of semiconductor portions separated from each other atpositions between adjacent data lines.
 18. The method of claim 16,wherein the thin film transistor panel includes a display area where thegate line intersects the data line and a peripheral area where endportions of the gate line and the data line are disposed, the slitsinclude first slits in the display area and in the peripheral area andsecond slits in a remaining area, and the first and the second slitshave different width and distance.
 19. The method of claim 10, whereinat least one of the gate line and the data conductive layer comprises alower film of Cr, Mo or Mo alloy and an upper film of Al or Al alloy.20. The method of claim 19, wherein the drain electrode comprises thelower film and the upper film and the method further comprises: removingthe upper film of the at least a portion of the drain electrode beforeforming the pixel electrode.
 21. The method of claim 10, wherein themask is aligned such that at least one of the slits overlaps a boundaryof the drain electrode.
 22. The method of claim 21, wherein the at leastone of the slits has a depression.
 23. The method of claim 10, whereinthe mask is aligned such that at least two of the slits are disposed outof the drain electrode.